Dynamic power management (DPM) has become an attractive solution for reducing power consumption in integrated circuits (ICs). DPM targets sub-circuits (e.g., circuit blocks) that sometimes perform tasks for short periods of time and enables the system to change power supply levels to those sub-circuits, hence minimizing power consumption. Depending on the sub-circuit block and its purpose, the power supply can be turned off when the sub-circuit block is not needed, or its potential can be decreased when the sub-circuit block is to operate with lower performance. There are different detection and power supply control management techniques for DMP [H, Lee, “A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System”, IEEE Journal of Solid-State Circuits, Vol. 45, pp. 2227-2238, November 2010], [Lee, “Dynamic voltage frequency scaling method and apparatus,” U.S. Pat. No. 9,436,253, Sep. 6, 2016], and their efficacy may depend on the application.
Some DPM schemes control the operation and supply levels of digital circuits [L. Benini and G. DeMicheli, “Dynamic power management: design, techniques, and CAD tools”, Springer Science+Business Media, LLC, New York, 1998], but DPM can also be used in analog circuits with a single power supply with a voltage lower than the maximum tolerance of devices such as transistors. Hence, turning off or reducing the power supply may not compromise the reliability of the system. As an example, a method proposed by Y. Tsividis, et. al., “Dynamic Power Management of Analog Signal Processors”, U.S. Pat. No. 7,436,251 B2, Oct. 14, 2008, selects the signal path according to the signal level to optimize the power consumption. This method, however, does not provide a solution to power down circuits with multiple power supplies.